[Zope-Checkins] CVS: Zope3/lib/python/Zope/ComponentArchitecture/tests - testIToIRegistry.py:1.1.2.5

[Stephan Richter]

Update of /cvs-repository/Zope3/lib/python/Zope/ComponentArchitecture/tests
In directory cvs.zope.org:/tmp/cvs-serv17954/ComponentArchitecture/tests

Modified Files:
      Tag: Zope-3x-branch
	testIToIRegistry.py 
Log Message:
- It is now allowed to specify a list of factories when specifying a view.
  The factories are listed separated by one whitespace. I make this partial
  checkin to show what files were modified. Let me know whether the 
  modification is done at the right spot and I will add more unit tests and
  maybe abstract everything more to support more than one whitespace. I 
  would also like to know, whether there are other spots too where I should
  be making modifications.



=== Zope3/lib/python/Zope/ComponentArchitecture/tests/testIToIRegistry.py 1.1.2.4 => 1.1.2.5 ===
         reg.register(RequiredInterface, I6, A6)
 
-        assert reg.get(InputI, I1)().name() == 'A2'
-        assert reg.get(InputI, I2)().name() == 'A2'
-        assert reg.get(InputI, I3)().name() == 'A4'
-        assert reg.get(InputI, I4)().name() == 'A4'
-        assert reg.get(InputI, I5)().name() == 'A6'
-        assert reg.get(InputI, I6)().name() == 'A6'
+        assert reg.get(InputI, I1)[0]().name() == 'A2'
+        assert reg.get(InputI, I2)[0]().name() == 'A2'
+        assert reg.get(InputI, I3)[0]().name() == 'A4'
+        assert reg.get(InputI, I4)[0]().name() == 'A4'
+        assert reg.get(InputI, I5)[0]().name() == 'A6'
+        assert reg.get(InputI, I6)[0]().name() == 'A6'
 
         # Be sure that it doesn't matter in what order you register
         # non-conflicting adapters.
@@ -52,12 +52,15 @@
         reg.register(RequiredInterface, I4, A4)
         reg.register(RequiredInterface, I2, A2)
 
-        assert reg.get(InputI, I1)().name() == 'A2'
-        assert reg.get(InputI, I2)().name() == 'A2'
-        assert reg.get(InputI, I3)().name() == 'A4'
-        assert reg.get(InputI, I4)().name() == 'A4'
-        assert reg.get(InputI, I5)().name() == 'A6'
-        assert reg.get(InputI, I6)().name() == 'A6'
+        assert reg.get(InputI, I1)[0]().name() == 'A2'
+        assert reg.get(InputI, I2)[0]().name() == 'A2'
+        assert reg.get(InputI, I3)[0]().name() == 'A4'
+        assert reg.get(InputI, I4)[0]().name() == 'A4'
+        assert reg.get(InputI, I5)[0]().name() == 'A6'
+        assert reg.get(InputI, I6)[0]().name() == 'A6'
+
+        # XXX Need to make list tests as well
+
 
     def testBadIndirectRegistry(self):